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august 2000 rev. 3 - eco #13132 1 pcmcia flash memory card flg series pc card products features ? low cost low/medium density linear flash card ? supports 5v systems with 12v vpp. ? based on intel cmos components ? fast read performance - 150ns maximum access time ? x8/ x16 data interface ? quick-pulse programming algorithm - typical 10s byte-program ? 100,000 erase/program cycles ? pc card standard type i form factor wedc?s flg series flash memory cards offer low/medium density linear flash solid state storage solutions for code and data storage, high performance disk emulation and execute in place (xip) applications in mobile pc and dedicated (embedded) equipment. flg series cards conform to pcmcia international standard. the card?s control logic provides the system interface and controls the internal flash memories. card can be read/written in byte-wide or word-wide mode which allows for flexible integration into various systems. combined with file management software, such as flash translation layer (ftl), flg flash cards provide removable high-performance disk emulation. the flg series cards contain separate 2kb eeprom memory for card information structure (cis) which can be used for easy identification of card characteristics. the wedc flg series is based on intel 28f010 or 28f020 flash memories. note: standard options include attribute memory. cards without attribute memory are available. cards are also available with or without a hardware write protect switch. pcmcia flash memory card 256kilobyte through 5 megabyte (intel based) wedc?s flg series is designed to support from 2 to 20, 1mb or 2mb components, providing a wide range of density options. cards are based on the 28f010 (1mb) or 28f020 components which work with 5v vcc / 12v vpp applications. device codes are b4 h and bd h respectively. systems should be able to recognize both codes. cards utilizing the1mb components provide densities ranging from 256kb to 2.5mb in 256kb increments, cards utilizing 2mb components provide densities ranging from 512kb to 5mb in 512kb increments. in support of the pc card 95 standard for word wide access devices are paired. write, read and erase operations can be performed as either a word or byte wide operation . by multiplexing a0, ce1# and ce2#, 8-bit hosts can access all data on data lines dq0 - dq7. the flg series cards conform to the pc card standard (pcmcia) and jeida, providing electrical and physical compatibility. the pc card form factor offers an industry standard pinout and mechanical outline, allowing density upgrades without system design changes. wedc?s standard cards are shipped with wedc?s logo. cards are also available with blank housings (no logo). the blank housings are available in both a recessed (for label) and flat housing. please contact wedc sales representative for further information on custom artwork. general description architecture overview
august 2000 rev. 3 - eco #13132 2 pcmcia flash memory card flg series pc card products block diagram device type manuf id device id 28f010 89 h b4 h 28f020 89 h bd h data bus d8-d15 vcc device 18 device 1 csl9 device 2 csl1 csl0 device pair 0 device pair 1 device 3 device pair 9 data bus q0-q7 i/o buffer control vcc data bus d0-d7 device 19 data bus q8-q15 device 0 q0-q7 wr# csl9 rd# c9 att enable csl0 c0 control logic pcmcia interface ctrl attrib. mem cis eeprom 2kb we# oe# ce2# ce1# reg# a0 wp address bus control address bus address buffer array address bus a1-a21(22) a1-a17(18) low high csh9 c9 csh0 c0 csh9 csh1 csh0 vcc vcc vpp2 vpp1 supported components (max 20 x): 28f020 - max 5mb 28f010 - max 2.5mb bvd1 bvd2 vs1 vs2 open open vcc cd1# cd2# gnd vcc wait#
august 2000 rev. 3 - eco #13132 3 pcmcia flash memory card flg series pc card products pinout notes: 1. wait#, bvd1 and bvd2 are driven high for compatibility 2. shows density for which specified address bit is msb. higher order address bits are no connects (i.e. 4mb a21 is msb a22 - a25 are nc). 3. for the 3mb card the memory will wrap at the 4mb boundary, for the 5mb card the memory will wrap at the 8mb boundary. mechanical 54.0mm 0.10 (2.126?) 10.0mm min (0.400?) 1.6mm 0.05 (0.063?) 1.0mm 0.05 (0.039?) 1.0mm 0.05 (0.039?) 3.3mm t1 (0.130?) t1=0.10mm interconnect area t1=0.20mm substrate area interconnect area 10.0mm min (0.400?) 3.0mm min 85.6mm 0.20 (3.370?) substrate area pin signal name i/o function active pin signal name i/o function active 1 gnd ground 35 gnd ground 2 dq3 i/o data bit 3 36 cd1# o card detect 1 low 3 dq4 i/o data bit 4 37 dq11 i/o data bit 11 4 dq5 i/o data bit 5 38 dq12 i/o data bit 12 5 dq6 i/o data bit 6 39 dq13 i/o data bit 13 6 dq7 i/o data bit 7 40 dq14 i/o data bit 14 7 ce1# i card enable 1 low 41 dq15 i data bit 15 8 a10 i address bit 10 42 ce2# i card enable 2 low 9 oe# i output enable low 43 vs1 o voltage sense 1 n.c. 10 a11 i address bit 11 44 rfu reserved 11 a9 i address bit 9 45 rfu reserved 12 a8 i address bit 8 46 a17 i address bit 17 256kb(2) 13 a13 i address bit 13 47 a18 i address bit 18 512kb(2) 14 a14 i address bit 14 48 a19 i address bit 19 1mb(2) 15 we# i write enable low 49 a20 i address bit 20 2mb(2) 16 rdy/bsy # o ready/busy n.c. 50 a21 i address bit 21 4mb(2,3) 17 vcc supply voltage 51 vcc supply voltage 18 vpp1 prog. voltage 52 vpp2 prog. voltage 19 a16 i address bit 16 53 a22 i address bit 22 8mb(2,3) 20 a15 i address bit 15 54 a23 i address bit 23 n.c. 21 a12 i address bit 12 55 a24 i address bit 24 n.c. 22 a7 i address bit 7 56 a25 i address bit 25 n.c. 23 a6 i address bit 6 57 vs2 o voltage sense 2 n.c. 24 a5 i address bit 5 58 rst i card reset n.c. 25 a4 i address bit 4 59 wait# o extended bus cycle low(1) 26 a3 i address bit 3 60 rfu reserved 27 a2 i addres s bit 2 61 reg# i attrib mem select 28 a1 i addres s bit 1 62 bvd2 o bat. volt. detect 2 (1) 29 a0 i addres s bit 0 63 bvd1 o bat. volt. detect 1 (1) 30 dq0 i/o data bit 0 64 dq8 i/o data bit 8 31 dq1 i/o data bit 1 65 dq9 i/o data bit 9 32 dq2 i/o data bit 2 66 dq10 o data bit 10 33 wp o write potect high 67 cd2# o card detect 2 low 34 gnd ground 68 gnd ground
august 2000 rev. 3 - eco #13132 4 pcmcia flash memory card flg series pc card products symbol type name and function a0 - a25 input address inputs: a0 through a25 enable direct addressing of up to 64mb of memory on the card. signal a0 is not used in word access mode. the memory will wrap at the card density boundary (see pinout, note 3). the system should not try to access memory beyond the card density. a25 is the most significant bit. a23 ? a25 are not connected. dq0 - dq15 input/output data input/output: dq0 through dq15 constitute the bi- directional databus. dq0 ? dq7 constitute the lower (even) byte and dq8 ? dq15 the upper (odd) byte. dq15 is the msb. ce1#, ce2# input card enable 1 and 2: ce1# enables even byte accesses, ce2# enables odd byte accesses. multiplexing a0, ce1# and ce2# allows 8-bit hosts to access all data on dq0 - dq7. oe# input output enable: active low signal gating read data from the memory card. we# input write enable: active low signal gating write data to the memory card. rdy/bsy# n.c. ready/busy output: indicates status of internally timed erase or program algorithms. this signal is not connected. cd1#, cd2# output card detect 1 and 2: provide card insertion detection. these signals are internally connected to ground on the card. the host shall monitor these signals to detect card insertion (pulled-up on host side). wp output write protect: write protect reflects the status of the write protect switch on the memory card. wp set to high = write protected, providing internal hardware write lockout to the flash array. if card does not include optional write protect switch, this signal will be pulled low internally indicating write protect = "off". vpp1 program/erase power supply: provides programming voltages 12.0v for lower byte (d0 ? d7) memory components. vpp2 program/erase power supply: provides programming voltages 12.0v for upper byte (d8 ? d15) memory components. vcc card power supply: (5.0v). gnd card ground reg# input attribute memory select : active low signal, enables access to attribute memory plane, occupied by card information structure and card registers. rst n.c. reset: active high signal for placing cards in power-on default state. this signal is not connected. wait# output wait: this signal is pulled high internally for compatibility. no wait states are generated. bvd1, bvd2 output battery voltage detect: these signals are pulled high to maintain sram card compatibility. vs1, vs2 output voltage sense: notifies the host socket of the card's vcc requirements. vs1 and vs2 are open to indicate a 5v card. rfu reserved for future use n.c. no internal connection to card: pin may be driven or left floating card signal description read function common memor y a ttribute memor y function mode / ce2 / ce1 a0 /oe /we / reg d15-d8 d7-d0 / reg d15-d8 d7-d0 standby mode hhxxx x high-z high-z x high-z high-z byte access (8 bits) hlllh h high-z even-b y te l high-z even-b y te hlhlh h high-z odd-byte l high-z not valid word access (16 bits) llxlh h odd-b y te even-b y te l not valid even-b y te odd-byte only access lhxlh h odd-b y te high-z l not valid high-z write function * standby mode hhxxx x xx x xx byte access (8 bits) hllhl h xeven-b y te l x even-b y te hlhhl h xodd-byte l xx word access (16 bits) llxhl h odd-b y te even-b y te l x even-b y te odd-byte only access lhxhl h odd-b y te x l xx functional truth table * require proper programming voltages (vpp1, vpp2). program or erase with an invalid vpp should not be attempted.
august 2000 rev. 3 - eco #13132 5 pcmcia flash memory card flg series pc card products absolute maximum ratings (1) operating temperature ta (ambient) commercial 0c to +60 c industrial -40c to +85 c storage temperature commercial -30c to +80 c industrial -40c to +85 c voltage on any pin relative to vss -0.5v to vcc+0.5v vcc supply voltage relative to vss -0.5v to +7.0v note: (1) stress greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. s y mbol parameter densit y notes t yp (3) max units test conditions i ccr vcc read current all 10 30 ma vcc = vccmax tc y cle = 150ns , cmos levels i ccw vcc program current all 1.0 10 ma programming in progress i ppw vpp program current all vpp = 12v 8.0 30 ma vpp=vpph programming in progress i cce vcc erase current all 5.0 15 ma erasure in progress i ppe vpp erase current all vpp = 12v 10 30 ma vpp=vpph erasure in progress 256kb 512kb 100 1mb 2mb 3mb 4mb i ccs ( cmos ) vcc standby current 5mb a vcc = vccmax control signals = vcc cmos levels notes: 1. all currents are rms values unless otherwise specified. iccr, iccw and icce are based on byte wide operations. for 16 bit operation values are double. 2. control signals: ce 1 #, ce 2 #, oe#, we#, reg#. 3. typical: vcc = 5v, t = +25oc. cmos test conditions: vcc = 5v 5%, vil = vss 0.2v, vih = vcc 0.2v dc characteristics (1) s y mbol parameter notes min max units test conditions i li input leakage current 1 1.0 a vcc = vccmax vin =vcc or vss i lo output leakage current 1 10 a vcc = vccmax vout =vcc or vss v il input low voltage 1 0 0.8 v v ih input high voltage 1 0.7vcc vcc+0.5 v v ol output low voltage 1 0.4 v iol = 3.2ma v oh output high voltage 1 vcc-0.4 vcc v ioh = -2.0ma v lko vcc erase/program lock voltage 12.5 v notes: 1. values are the same for byte and word wide modes for all card densities. 2. exceptions: leakage currents on ce1#, ce2#, oe#, reg# and we# will be < 500 a when vin = gnd due to internal pull-up resistors.
august 2000 rev. 3 - eco #13132 6 pcmcia flash memory card flg series pc card products 150ns 200ns symbol (pcmcia) parameter min max min max unit t c (r) read cycle time 150 200 ns t a (a) address access time 150 200 ns t a (ce) card enable access time 150 200 ns t a (oe) output enable access time 75 100 ns t su (a) address setup time 20 20 ns t su (ce) card enable setup time 0 0 ns t h (a) address hold time 20 20 ns t h (ce) card enable hold time 20 20 ns t v (a) output hold from address change 00ns t dis (ce) output disable time from ce# 60 60 ns t dis (oe) output disable time from oe# 60 60 ns t en (ce) output enable time from ce# 5 5 ns t en (oe) output enable time from oe# 5 5 ns ac characteristics note: ac timing diagrams and characteristics are guaranteed to meet or exceed pcmcia 2.1 specifications. read timing diagram note 1 note 1 a [25::0], /reg /ce1, /ce2 /oe d[15::0] tc(r) ta(a) th(a) tv(a) ta(ce) tsu(ce) th(ce) ten(oe) ta(oe) tsu(a) data valid tdis(ce) tdis(oe) read timing parameters note: signal may be high or low in this area.
august 2000 rev. 3 - eco #13132 7 pcmcia flash memory card flg series pc card products 150ns 200ns symbol (pcmcia) parameter min max min max unit t c w w rite c y cle time 150 200 ns t w (we) w rite pulse width 80 120 ns t su (a) a ddress setu p time 20 20 ns t su (a-weh) a ddress setu p time for we # 100 100 ns t su (ce- weh) card enable setu p time for we# 100 100 ns t su (d-weh) data setu p time for we # 50 50 ns t h (d) data hold time 20 20 ns t rec (we) w rite recover time 20 20 ns t dis (we) out p ut disable time from we # 60 60 ns t dis (oe) out p ut disable time from oe # 60 60 ns t en (we) out p ut enable time from we # 55ns t en (oe) out p ut enable time from oe # 55ns t su (oe-we) out p ut enable setu p from we # 10 10 ns t h (oe-we) out p ut enable hold from we # 10 10 ns t su (ce) card enable setu p time from oe# 0 0 ns t h (ce) card enable hold time 20 20 ns note: ac timing diagrams and characteristics are guaranteed to meet or exceed pcmcia 2.1 specifications. write timing diagram write timing parameters th (o e -w e ) note 1 /c e 1 , /c e 2 note 1 ts u (c e -w e h ) tc(w ) a [2 5::0 ], /r e g tw (w e ) td is(w e ) th (d ) d[15::0](din) data input ts u (a ) ts u (a -w e h ) /o e tsu (c e ) tsu(d -w e h ) trec(w e ) th (c e ) tsu (o e -w e ) td is(o e ) d[15::0](dout) ten (o e ) te n(w e ) note 2 note 2 /w e notes: 1. signal may be high or low in this area. 2. when the data i/o pins are in the output state, no signals shall be applied to the data pins (d15 - d0) by the host system.
august 2000 rev. 3 - eco #13132 8 pcmcia flash memory card flg series pc card products parameter notes min typ (1) max units 28f010 1,2,4 2 12.5 chip program time 28f020 1,2,4 4 25 sec 28f010 1,3,4 1 10 chip erase time 28f020 1,3,4 2 30 sec data write and erase performance notes: 1. typical: nominal voltages and t a = 25oc. 2. minimum byte programming time excluding system overhead is 16 s (10s program + 6s write recovery), while maximum is 400s/byte (16 s x 25 loops allowed by algorithm). max chip programming time is specified lower than the worst case allowed by the programming algorithm since most bytes program significantly faster than the worst case byte. 3. excludes 00h programming prior to erasure. 4. excludes system-level overhead. vcc = 5v 5%, vpp1 = vpp2=12.0v, t a = 25oc
august 2000 rev. 3 - eco #13132 9 pcmcia flash memory card flg series pc card products cis information for flg series cards address value description address value description 00h 01h cistpl_device 4ah 32h 2 02h 03h tpl_link 4ch 35h 5 04h 53h flash = 150ns (device writable) 4eh 36h 6 52h flash = 200ns (device writable) 35h 5 06h 0ch card size: 256kb 31h 1 05h 512kb 32h 2 0dh 1mb 30h 0 06h 2mb 30h 0 2dh 3mb 31h 1 0eh 4mb 30h 0 4dh 5mb 30h 0 08h ffh end of device 32h 2 0ah 18h cistpl_jedec_c 30h 0 0ch 02h tpl_link 30h 0 0eh 89h intel - id 33h 3 10h b4h intel 28f010 - id 30h 0 bdh intel 28f020 - id 30h 0 12h 17h cistpl_device_a 34h 4 14h 03h tpl_link 30h 0 16h 42h eeprom - 200ns 30h 0 18h 01h device size = 2kbytes 35h 5 1ah ffh end of tuple 50h 46h f 1ch 1eh cistpl_devicegeo 52h 4ch l 1eh 06h tpl_link 54h 47h g 20h 02h dgtpl_bus 56h 30h 0 22h 11h dgtpl_ebs 58h 32h 2 24h 01h dgtpl_rbs 30h 0 26h 01h dgtpl_wbs 36h 6 28h 01h dgtpl_part 5ah 2dh - 2ah 01h flash device 5ch 2dh - non-interleaved 5eh 2dh - 2ch 20h cistpl_manfid 60h 31h 1 2eh 04h tpl_link(04h) 62h 35h 5 30h f6h edi tplmid_manf: lsb 64h 20h space 32h 01h edi tplmid_manf: msb 66h 00h end text 34h 00h lsb: number not assigned 68h 43h c 36h 00h msb: number not assigned 6ah 4fh o 38h 15h cistpl_vers1 6ch 50h p 3ah 47h tpl_link 6eh 59h y 3ch 05h tpllv1_major 70h 52h r 3eh 00h tpllv1_minor 72h 49h i 40h 45h e 74h 47h g 42h 44h d 76h 48h h 44h 49h i 78h 54h t 46h 37h 7 48h 50h p
august 2000 rev. 3 - eco #13132 10 pcmcia flash memory card flg series pc card products cis information for flg series cards -( cont .) address value description 7ah 20h space 7ch 45h e 7eh 4ch l 80h 45h e 82h 43h c 84h 54h t 86h 52h r 88h 4fh o 8ah 4eh n 8ch 49h i 8eh 43h c 90h 20h space 92h 44h d 94h 45h e 96h 53h s 98h 49h i 9ah 47h g 9ch 4eh n 9eh 53h s a0 h 20h space a2 h 49h i a4 h 4eh n a6 h 43h c a8 h 4fh o aah 52h r ac h 50h p aeh 4fh o b0h 52h r b2h 41h a b4h 54h t b6h 45h e b8h 44h d bah 20h space bch 00h end text beh 31h 1 c0h 39h 9 c2h 39h 9 c4h 37h 7 c6h 00h end text c8h ffh end of list cah ffh cis tp l_ end dch 00h in val id ad d r ess
august 2000 rev. 3 - eco #13132 11 pcmcia flash memory card flg series pc card products edi company name lot code / trace number date code part number product marking wed 7p001flg0200c15 c995 9915 note: some products are currently marked with our pre-merger company name/acronym (edi). during our transition period, some products will also be marked with our new company name/acronym (wed). starting october 2000 all pcmcia products will be marked only with the wed prefix. card capacity 001 1mb packaging option 00 standard, type 1 pc card p standard pcmcia r ruggedized pcmcia card family and version - see card family and version info. for details (next page) temperature range c commercial 0c to +70c i industrial -40c to +85c card access time 15 150ns 25 250ns card technology 7flash 8sram part numbering 7 p 001 flg02 00 c 15
august 2000 rev. 3 - eco #13132 12 pcmcia flash memory card flg series pc card products card family and version information flg 01-flg04 based on 28f010 flg01 no attribute memory, no write protect flg02 with attribute memory, no write protect flg03 no attribute memory, with write protect flg04 with attribute memory, with write protect example p/n 7p xxx flg 02 ss t zz flg 05-flg08 based on 28f020 flg05 no attribute memory, no write protect flg06 with attribute memory, no write protect flg07 no attribute memory, with write protect flg08 with attribute memory, with write protect example p/n 7p xxx flg 06 ss t zz 7p xxx flgyy ss t zz where xxx: 256 1) 256kb 512 512kb 001 1mb 002 2mb 003 2) 3mb 004 2) 4mb 005 2) 5mb 1) available only with 28f010 2) available only with 28f020 flgyy: card version (see card family and version information) ss: 00 wedc silkscreen 01 blank housing, type i 02 blank housing, type i recessed t: c commercial i** industrial zz: 15 150ns 20 200ns note: options with intermediate memory capacities, without attribute memory and with hardware write protect switch are available. ** denotes advanced information. ordering information
august 2000 rev. 3 - eco #13132 13 pcmcia flash memory card flg series pc card products revision history: rev level description date rev 0 initial release march 6, 1998 rev 1 logo change may 27, 1999 rev 2 added page 11 may 31, 2000 changed page header rev 3 corrected timing errors august 1, 2000 on pg. 6 & 7 white electronic designs corporation one research drive, westborough, ma 01581, usa tel: (508) 366 5151 fax: (508) 836 4850 www.whiteedc.com

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